1. Field of the Invention
The present invention generally relates to communications networks employing an ATM (Asynchronous Transfer Mode) transmission system. More particularly, the present invention is concerned with an ATM cell error processing system which detects an error in an ATM cell and processes such a defective ATM cell in a predetermined manner.
2. Description of the Prior Art
Recently, there has been considerable activity in the development of ATM transmission systems. As is well known, ATM cells have a format as shown in FIG. 1. FIG. 1-(a) shows an ATM layer data format, and Fig:. 1-(b) shows an AAL (ATM Adaptation Layer) data format. In the AAL, there are four types of data formats with respect to services in upper layers. FIG. 1-(b) shows a data format of a class 3 AAL, which is one of the four types of data formats, and which provides connection-oriented data communications services
The ATM cell consists of a header having five bytes (B), and an information field having 48 bytes. The ATM header includes a four-bit (b) undefined GFC (Generic Flow Control) field, an 8-bit VPI (Virtual Path Identifier) field, and a 16-bit VCI (Virtual Channel Identifier) field. The VPI and VCI are basic data used when an ATM switch determines a route. Further, the ATM cell includes a 2-bit PT (Payload Type), a one-bit RS (Reserved) field, a one-bit CLP (Cell Loss Priority) field, and an 8-bit HEC (Header Error Control) field. Data in the CLP field shows whether or not the ATM cell should be discarded. The HEC is a CRC (Cyclic Redundancy Check) for the ATM header.
The ATM header consists of a total of 40 bits, which is equal to five bytes. The information field contains 44 bytes of information and an additional four bytes of data, as shown in FIG. 1-(b). The four-byte data contained in the information field includes two bits of data representing a segment type (ST), four-bit data showing a sequence number (SN), 10 received bits (RES), six-bit length identifier (LI) data, and ten bits representing CRC data. The segment type (ST) data is used for identifying the beginning and end of a message. The sequence number (SN) data represents the position of the cell in the message. The length identifier (LI) data represents the actual length of information. The 10-bit CRC data is error correction code for the information field.
FIG. 2 shows an overview of an ATM switching system, which comprises an ATM switch (or TC layer terminating equipment), and a message processing unit 2. The message processing unit 2 comprises a sender-side cell processor 2a, and a receiver-side cell processor 2b. The message processing unit 2 exchanges ATM cells with protocol data units (messages) in an upper layer. The sender-side cell processor 2a segments a message from the upper layer into units, each consisting of 44 bytes, and forms ATM cells conforming to the format shown in FIG. 1. The receiver-side cell processor 2b assembles ATM cells from the ATM switch 1 into a message conforming to the upper layer.
The receiver-side cell processor 2b has a function of detecting an error in cell unit in order to determine whether or no teach cell is correct. FIG. 3 shows types of cell errors. In FIG. 3, three cell errors to be detected are defined for the ATM layer, and four cell errors to be detected are defined for the AAL.
FIG. 4 is a diagram showing an overview of a conventional ATM cell error processing system. As shown in FIG. 4, the system includes a plurality of serially connected error processors 10 equal in number to the types of cell errors to be detected. The error processors 10 operate independently from each other, and each have the function of detecting a predetermined cell error, discarding an error cell and notifying a failure monitor unit 20 of detected error information.
FIG. 5 shows the structure of each of the error processors 10 shown in FIG. 4. Each error processor 10 comprises an error check unit 21, a cell buffer 22 and an error cell discarding unit 23. The error check unit 21 receives an ATM cell and determines whether or not the ATM cell has a predetermined error. During this determination process, the ATM cell is queued in the cell buffer 22. If the error check unit 21 determines that the ATM cell has the predetermined error, it outputs a cell discarding instruction to the error cell discarding unit 23. In response to receipt of the cell discarding instruction, the error cell discarding unit 23 discards the ATM cell. The error check unit 21 then informs the failure monitor unit 20 of the result of the check.
However, the conventional ATM cell error processing systems as described above have the following disadvantages.
Firstly, the cell buffer 22 must be provided in each error processor 10 in order to detect an error cell and discard it. Hence, a large quantity of hardware is needed to configure the system and a large amount of cell delay is introduced. It should be noted that the cell error detecting processes are sequentially carried out by the error processors 10 in a predetermined order, because if a cell error has been detected during a series of error detecting processes, it is no longer necessary to execute the remaining cell error detecting processes. For example, the procedure for detecting cell errors checks the fields in the order HEC, VCI, PT, CRC, ST, SN, MID and LI.
Secondly, with respect to some check items, it is necessary to determine whether or not each ATM cell has cell errors defined in these check items, but is not necessary to discard each ATM cell even if the cell errors have been detected. The above is called an error masking function. In order to establish the error masking function, the system shown in FIG. 4 is modified, as shown in Fig, 6. The failure monitor unit 20 outputs mask instructions to the error processors 10 which are to execute the error masking function. However, the system shown in FIG. 6 has the following disadvantages. The control process of the failure monitor unit 20 is very complicated because it must individually output mask instructions to the error processors 10. Further, the ATM cells must be held in the cell buffers 22 even when these ATM cells are defective but not discarded.
Thirdly, an error editing process based on the results of error check is very complicated or impossible because the error processors 10 separately generate the cell discarding instructions. For example, it is impossible to discard an ATM cell when it has a plurality of errors selected from among the predetermined cell error types.